Low Power 1-Bit Full Adder Using Full-Swing Gate Diffusion Input Technique
This paper presents a design which provides full swing output for logic 1 and logic 0 for 1-bit full adder cell and reduces power consumption, delay, and area. In this design full adder consists of two XOR gate cells and one cell of 2x1 multiplexer (MUX). The performance of the proposed design compared with the different logic style for full ... إقراء المزيد